Impulse C is one of the most widely used software to FPGA hardware optimizing compilers. It has been used in over 2,000 designs by clients as diverse as NASA, Sony and Wall Street Banks. Impulse CoDeveloper is compatible with > 90% of FPGAs, and available processor cores. Impulse CoDeveloper also produces synthesizable VHDL or Verilog compatible with many other tools.

Impulse CoDeveloper enables Software Developers and Hardware Engineers to offload processor bound functions into FPGA. Multiple modes are supported. Projects can be exported as pure parallel-hardware running in optimized multiple streaming functions. Projects can be partitioned between FPGA logic and optional ARM or other on-board processors for System-on-Chip solutions. Projects can be partitioned between FPGA and the systems microprocessor, running code or commands over PCIe or other high speed interfaces. CoDeveloper easily integrates with current software flows. CoDeveloper offers extensive tutorials (both video and print) and a rich library of free and for-pay reference designs.

Impulse CoValidator(tm) HDL Test Bench Generator Saves Design Time — The intermediate file format of Impulse CoDeveloper is synthesizable VHDL. CoValidator generates HDL compatible with all IEEE-compliant VHDL simulators, and also generates scripts for popular HDL simulators such as Mentor’s ModelSim(r) or Aldec’s Active-HDL(r), allowing you to generate HDL test benches and launch simulation with just a few keystrokes. Catch errors before place-and-route, saving hours, days or even weeks of development time. Generate an HDL test bench, data files, and simulator scripts for hardware validation and hardware/software equivalency checking.

Profiling and partitioning occurs within Visual Studio, GCC or Eclipse. Visualization tools such as stage analysis, and the Applications Manager (shown) make it easier to understand how data buffers will work and how the code will propagate into hardware. Process Flow Visualization is a feature of the debug environment within Impulse. This helps illustrate how streaming processes and modules interconnect.Process Synchronization via Streams, Signals or Registers. Processes are independently synchronized with multiple methods of process-to-process communications are supportedDebug and verification occurs at multiple levels. Functional simulations within a debugger such as Visual Studio to verify basic equivalency. Exporting VHDL to a simulator adds cycle accurate simulation. (see CoValidator on left)Compilation and optimization utilizes communicating C-language processes to create parallelism. They support data flow and message-based communications. They support parallelism at the application level and at the level of individual processes. And they allow simulation and debugging of parallel software processes. 

Buy the Book!. A Textbook and teaching materials are available to enable you to either learn about Impulse or to integrate Impulse into college or graduate level teaching. Over 6,000 copies sold. Dozens of Masters projects completed with Impulse C from Universities in Poland, Japan, China, Germany, UK and the US. The book is available new or used through Amazon and other book sellers. Teaching materials are available upon request (use our contact form). Impulse also offers on- and off-site training.